The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
The decreased geometry size leads to challenges in fabrication. For example, as geometry sizes continue to decrease, it is more difficult to achieve critical dimension (CD) uniformity for semiconductor devices. For example, poor CD uniformity may be a result of variations in topography. Poor CD uniformity may lead to undesirable drifting of drain currents and threshold voltages of transistors. Traditionally, when geometry sizes are relatively large, the topography variations may have a negligible effect on the CD uniformity. However, as geometry sizes become smaller and smaller, even slight variations in topography may have a detrimental effect on CD uniformity. Furthermore, to a semiconductor foundry, it may need to interact with multiple customers whose devices each have their own unique topography. Consequently, the CD uniformity issue may be more pronounced for the semiconductor foundry.
Traditional fabrication method of controlling CD uniformity are expensive and tend to suffer from undesired lateral etching problems which may limit the effectiveness of the CD uniformity control. Therefore, while traditional methods of CD uniformity control have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.